The invention is directed to integrated circuit arrangements having at least one MOS transistor and to methods for the manufacture thereof.
In integrated circuit arrangements, MOS transistors and logic gates are currently usually realized in a planar silicon technology, whereby source, channel region and drain are laterally arranged. The channel lengths that can be achieved are thereby dependent on the resolution of the optical lithography employed and on tolerances in the structuring and alignment. Typical channel lengths of 0.6 .mu.m are achieved in the 16 M generation, 0.35 .mu.m in the 64 M generation.
A further shortening of the channel lengths of MOS transistors is desirable, for example in circuit arrangements in which fast switching events are required, which is usually the case in logic processing. The packing density of a circuit arrangement can also be increased by MOS transistors with short channel lengths. The space-consuming, large channel width that is otherwise necessary can be foregone by employing short channel lengths, specifically when processing high current intensities in, for example, line drivers.
Some possibilities for reducing the channel length have been disclosed. However, the step from the fabrication of a single unit to mass production is time-consuming and costly, specifically in semiconductor technology. New, improved circuit structures are therefore especially attractive for semiconductor manufacture when it is only the existing know-how that has to be recoursed, insofar as possible. This economic aspect is not satisfied by the prior proposals for realizing shortened channel lengths.
For example, it was proposed that shorter channel lengths be achieved in planar MOS transistors by replacing the optical lithography with electron beam lithography, a resolution of which is significantly better (see, for example, T. Mizuno, R. Ohba, IEDM Tech. Dig., p. 109 (1996)). Individual, functional MOS transistors with channel lengths as short as 50 nm have hitherto been successfully produced with an electron beam printer on a laboratory scale. Although known layouts that must merely be miniaturized can be employed with this technology, electron beam lithography is slow; as a result thereof, it seems unsuitable for employment in semiconductor manufacture.
Masks are under-etched, i.e. hollowed out underneath, by isotropic over-etching of layers, as a result of which smaller structural sizes than those belonging to lithography can likewise be produced. However, it is difficult to achieve reproducible results with this technique, for which reason it will presumably also not be employed on a broad basis in semiconductor manufacture.
Further possibilities of obtaining short channel lengths are available given a channel path that is perpendicular to the surface of the circuit arrangement instead of parallel. Transistors having a perpendicular channel course are referred to as "vertical transistors". The channel length is thereby determined by the layer thickness of the channel region and is thus independent of the resolution of the lithography employed.
A circuit arrangement of integrated MOS transistors has been disclosed whose source, channel region and drain are stacked above one another as layers (see German Letters Patent DE 4340967 C1). The contacting of source, drain and gate electrode of such an MOS transistor, accordingly, occurs differently than given planar transistors. At least two of the layers are grown by epitaxy. A depression that has its sidewalls provided with a gate dielectric and a gate electrode is etched into this layer sequence. A channel length as short as less than 50 nm is achieved by this procedure. What is especially disadvantageous is the increased process expense when incorporating this circuit arrangement into semiconductor manufacture due to the manufacturing method that clearly differs from the traditional manufacturing method.